Publications

Please note: We recently moved our website from an older platform (Confluence) to the open source WordPress. It is our intent to provide full documentation of all unpublished and student reports here. For recent (to-be-published) work, a draft may be available until it is officially published at a conference, either here or under the Research section. Otherwise, at least an abstract is available here. We will upload the files over a period of time.

Here are the major sections: (these will be separated and made easily accessible soon):

  • Technical Reports: Earlier ones (through 2009) are listed here — recent ones to be included
  • Student Reports: most earlier ones are here; the recent ones (2010 on) are actually team project reports with comprehensive zip files. These will be uploaded during Spring ’13.
  • Papers: Earlier ones are listed here. For 2010-2013: To be included. See the Research section.

Technical Reports


Papers 2009


Student Reports


Tutorials

  • Norona, C., TUTORIAL – EASy68k, tutorial TU-2, for Professor Shankar’s course, CEN4214 – Software/Hardware Codesign, 2009.


Papers 2008


Papers 2007

  • Agarwal, A., Shankar, R., A Concurrency Model for Network on Chip Design Methodology International Journal of Modeling and Simulation (Acepted – to be published).
  • Agarwal, A., Mustafa, M., Shankar, R., Pandya, A.S., Lho, Y., A Deadlock Free Router Design for Network on Chip Architecture, Journal of the Korea Institute of Maritine Information adn Communication Sciences, Vol. 11, No. 4, pp. 696-706, April 2007
  • Agarwal, A., Shankar, S., Iskander, C., NoC Model in System Level Modeling Environment: MLDesigner, Journal of Engineering, Computing and Architectures” (Acepted – to be published).
  • Agarwal, A., Iskander, C., Shankar, R., Survey of NoC Architectures and Contributions, Journal of Engineering, Computing and Architectures” (Acepted – to be published).
  • Shankar, R., Kalva, H., Agarwal, A., Jain, A., Annotation Methods for Embedded Systems, IEEE International Conference on Portable Information Device, Orlando, FL April 2007.
  • Huang, S., Shankar, R., Mangs, J., Towards Strategic Design Reuse by Leveraging Commodity and managing Variability, 1st Annual IEEE Systems Conference, Hawaii, April 2007.


Papers 2006

  • Agarwal, A., Shankar, R., Pandya, A.S., Embedding Intelligence into EDA Tools to Meet the Future Technology Trends, Integrated Intelligent Systems for Engineering Design, Edited by Dr. Xuan F Zha, National Institute of Standards and Technology, USA & Dr. R. J. Howlett, University of Bringhton, UK
  • Agarwal, A., Shankar, R., A Concurrency Model for NOC Design Methodology, IEEE Conference of High Performance Computing, Massachusetts Institute of Technology, September 2006
  • Agarwal, A., Pandya, A. S., Lho, Y., NOC Architecture Design Methodology, Journal of Korea Institute of matitime Information and Communication Sciences, Vol.1, pp. 57-64, August 2006
  • Agarwal, A., Pandya, A.S., Lho, Y., Low Power High Frequency Data Transfer for a RISC and CISC Processor Using AdHoc Techniques, The International Journal of Korean Institute of Maritime Information and Communication Sciences, Vol. 10, No.2, pp. 321-327, August 2006.
  • Agarwal, A., Pandya, A.,Software Complexity Management for Real-Time Systems, International Journal of KIMICS, Vol 4, No. 1, pp.23-27, March 2006
  • Agarwal, A., Shankar, R., Kovalski, F., Modeling Concurrency on NOC Architecture with Symbolic Language: FSP, IEEE International Conference on Symbolic Methods and Applications to Circuit Design, October 2006
  • Agarwal, A., Mustafa, M., Shankar, R., Quality of Service Driven Communication Backbone Design for Network on Chip Architecture Design Methodology, IEEE Conference in Electrical and Computer Engineering, Canada, May 2006
  • Agarwal, A., Mustafa, M., Shankar, R., Pandya, A. S., Quality of Service Driven Communication Backbone Design for Network-on-Chip Architecture Design Methodology, IEEE Conference on Electrical and Computer Engineering, Canada, May 2006


Papers 2005

  • Agarwal, A., Shankar, R., A Layered Architecture for NOC Design Methodology, International Conference on parallel and Distributed Computing and Systems”, November 2005
  • Agarwal, A., Pandya. A., Lho, Y., Low Power Design of an ALU Using AdHoc Techniques, International Journal of Fuzzy Logic and Intelligent Systems, Vol. 5, No. 2, Jun 2005
  • Agarwal, A., Pandya. A., Lho, Y.,Biometrics for Person Authentication: A Survey, Journal of Korea Intelligent Information System Society, Vol. 11, No. 1, pp. 1-15, June 2005


Papers 2004

  • Agarwal, A., Pandya. A., Lho, Y., Low Power Design of a Neuroprocessor, International Journal of Fuzzy Logic and Intelligent Systems, Vol. 4, No. 1, pp. 79-81, Jun 2004


Older Publications

  • Ajmera, A.M., Shankar R., Masory, O., AMS Designer for Mechatronics, 2002 IEEE International Workshop on Behavioral Modeling and Simulation, BMAS 2002, Santa Rosa, CA, Oct. 6-8, 2002
  • Ajmera, A. M., Shankar, R., Masory, O., AMS Designer for Mechatronics, International Cadence Usergroup Conference 2002, Cadence Design Systems, San Jose, CA, Sep 15-19, 2002